IOMMU/ATS: fix maximum queue depth calculation
authorJan Beulich <jbeulich@suse.com>
Wed, 5 Dec 2012 08:52:14 +0000 (09:52 +0100)
committerJan Beulich <jbeulich@suse.com>
Wed, 5 Dec 2012 08:52:14 +0000 (09:52 +0100)
commitdda3fb206c1d0dbb350dc61bc97124c80f315083
tree54b6dbd987f21e4af2b7b6d80d27566f4f672db6
parente662eca49cf7c6ab16f874331b6893649b5cfee7
IOMMU/ATS: fix maximum queue depth calculation

The capabilities register field is a 5-bit value, and the 5 bits all
being zero actually means 32 entries.

Under the assumption that amd_iommu_flush_iotlb() really just tried
to correct for the miscalculation above when adding 32 to the value,
that adjustment is also being removed.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by Xiantao Zhang <xiantao.zhang@intel.com>
Acked-by: Wei Huang <wei.huang2@amd.com>
xen/drivers/passthrough/amd/iommu_cmd.c
xen/drivers/passthrough/ats.h
xen/drivers/passthrough/x86/ats.c